The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2023

Filed:

May. 17, 2021
Applicant:

Petalo Inc., Santa Clara, CA (US);

Inventors:

Naveen Kumar, San Jose, CA (US);

Seok Lee, San Jose, CA (US);

LingQi Zeng, San Jose, CA (US);

Assignee:

PETAIO INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/46 (2006.01); G11C 29/36 (2006.01); G11C 29/44 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 29/42 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3495 (2013.01); G11C 29/36 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01);
Abstract

A storage device includes 3D NAND including layers of multi-level cells. Test reads are performed by reading only LSB pages and reading layers in a repeating pattern of reading two and skipping two. A test read of a block is performed when its read count reaches a threshold. The counter threshold is updated according to errors detected during the test read such that the frequency of test reads increases with increase in errors detected. Counter thresholds according to errors may be specified in a table. The table may be selected as corresponding to a range of PEC values including the current PEC count of the 3D NAND. Each table further specifies a number of errors that will result in garbage collection being performed.


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