logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11580027 B1

PDFFull Text
Date of Patent:
Feb. 14, 2023

Filed:

Feb. 26, 2020

Multi-tile memory management mechanism

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zack S. Waters, Portland, OR (US);

Travis Schluessler, Berthoud, CO (US);

Michael Apodaca, Folsom, CA (US);

Ankur Shah, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Jaffery Watson Mendonsa & Hamilton LLP

Primary Examiner:

Aracelis Ruiz

Int. Cl.
CPC ...
G06F 12/0882 (2016.01); G06F 12/0837 (2016.01); G06F 12/1045 (2016.01); G06F 11/30 (2006.01); G06F 9/50 (2006.01); G06F 9/4401 (2018.01); G06F 9/54 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0882 (2013.01); G06F 9/4411 (2013.01); G06F 9/5016 (2013.01); G06F 9/544 (2013.01); G06F 11/3006 (2013.01); G06F 11/3037 (2013.01); G06F 12/0607 (2013.01); G06F 12/0837 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01);
Abstract

Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Find Patent Forward Citations

Quick Actions:

Waters, Zack. (2023). Multi-tile memory management mechanism (U.S. Patent No. 11580027). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11580027

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…