The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Mar. 28, 2022
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventor:

Yi-Chung Liang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01);
Abstract

A manufacturing method of a semiconductor device at least includes the following steps. A substrate having a stacked structure is provided. An epitaxy process is performed to form an epitaxial layer on the substrate on two sides of the stacked structure. A recess is forming on the two sides of the stacked structure, wherein the recess penetrates through the epitaxial layer, extends into the substrate, and has a tip located in the substrate. A source/drain region is formed in the recess, wherein a material of the source/drain region comprises silicon germanium. A spacer wall material layer is formed on the substrate. A portion of the stacked structure is removed to from a gate structure. A portion of the spacer wall material layer is removed to form a spacer wall on the epitaxial layer. A semiconductor device is also provided.


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