The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2023
Filed:
May. 13, 2021
Applicant:
Nanya Technology Corporation, New Taipei, TW;
Inventor:
Chin-Ling Huang, Taoyuan, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/823418 (2013.01); H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 29/4011 (2019.08); H01L 29/41725 (2013.01); H01L 29/41791 (2013.01); H01L 29/42316 (2013.01); H01L 29/42364 (2013.01); H01L 29/4933 (2013.01); H01L 29/518 (2013.01); H01L 2924/1304 (2013.01);
Abstract
The present application discloses a method for fabricating a semiconductor device includes providing a substrate, forming a gate stack on the substrate and a pair of heavily-doped regions in the substrate, forming a programmable contact having a first width on the gate stack, and forming a first contact having a second width, which is greater than the first width, on one of the pair of heavily-doped regions.