The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Mar. 18, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sungkweon Baek, Hwaseong-si, KR;

Taeyoung Kim, Seoul, KR;

Hakseon Kim, Seoul, KR;

Kangoh Yun, Hwaseong-si, KR;

Changhoon Jeon, Goyang-si, KR;

Junhee Lim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1041 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/4236 (2013.01); H01L 29/0653 (2013.01); H01L 29/66575 (2013.01); H01L 29/66659 (2013.01); H01L 29/7833 (2013.01);
Abstract

A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.


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