The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Jun. 07, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yun-Chi Wu, Tainan, TW;

Yu-Wen Tseng, Chiayi, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 29/423 (2006.01); H01L 27/12 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); B82Y 10/00 (2011.01); H01L 29/792 (2006.01); H01L 29/775 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); B82Y 10/00 (2013.01); H01L 27/1203 (2013.01); H01L 27/1237 (2013.01); H01L 29/068 (2013.01); H01L 29/0673 (2013.01); H01L 29/42344 (2013.01); H01L 29/42392 (2013.01); H01L 29/512 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66439 (2013.01); H01L 29/66469 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/775 (2013.01); H01L 29/792 (2013.01); H01L 27/11568 (2013.01);
Abstract

A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.


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