The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

May. 13, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joshua M. Rubin, Albany, NY (US);

Steven Lorenz Wright, Cortlandt Manor, NY (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 23/5381 (2013.01); H01L 23/5385 (2013.01); H01L 25/50 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.


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