The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2023

Filed:

Mar. 03, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Hideki Yamada, Yokohama, JP;

Masanobu Shirakawa, Chigasaki, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); H01L 27/11556 (2017.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 11/5621 (2013.01); H01L 27/11556 (2013.01);
Abstract

According to the one embodiment, a memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes: first and second memory cells stacked above a substrate; a first word line coupled to the first and second memory cells; a first bit line coupled to the first memory cell; and a second bit line coupled to the second memory cell. A first state read operation includes a first read operation for reading data from the first memory cell and a second read operation for reading data from the second memory cell. A first read voltage is applied to the first word line during a first period for executing the first read operation, and a second read voltage is applied to the first word line during a second period for executing the second read operation.


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