The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2023
Filed:
Nov. 30, 2018
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Jung-Chan Yang, Longtan Township, TW;
Ting-Wei Chiang, New Taipei, TW;
Jerry Chang-Jui Kao, Taipei, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Lee-Chung Lu, Taipei, TW;
Li-Chun Tien, Tainan, TW;
Meng-Hung Shen, Zhubei, TW;
Shang-Chih Hsieh, Yangmei, TW;
Chi-Yu Lu, New Taipei, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of fabricating an integrated circuit structure includes placing a first set of conductive structure layout patterns on a first layout level, placing a second set of conductive structure layout patterns on a second layout level, placing a first set of via layout patterns between the second set of conductive structure layout patterns and the first set of conductive structure layout patterns, and manufacturing the integrated circuit structure based on at least one of the layout patterns of the integrated circuit. At least one of the layout patterns is stored on a non-transitory computer-readable medium, and at least one of the placing operations is performed by a hardware processor. The first set of conductive structure layout patterns extends in a first direction. The second set of conductive structure layout patterns extends in the second direction, and overlap the first set of conductive structure layout patterns.