The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2023
Filed:
Sep. 26, 2022
Monolithic 3d Inc., Klamath Falls, OR (US);
Zvi Or-Bach, Haifa, IL;
Zeev Wurman, Palo Alto, CA (US);
Monolithic 3D Inc, Klamath Falls, OR (US);
Abstract
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes logic and the second level includes memory; and then obtaining a first placement of at least portion of the second level, where the first placement includes placement of a first memory array, where the Circuit includes a plurality of connections between the first level and the second level; and performing a second placement, where performing the second placement includes placing the first logic circuit based on the first placement of the first memory array, where the performing a second placement includes using a placer executed by a computer, where the placer is a part of a Computer Aided Design tool, and where the logic includes a first logic circuit configured to read data from the first memory array.