The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Feb. 02, 2022
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Kuan Zhou, Newton, MA (US);

David Da-Wei Lin, Westborough, MA (US);

Vladimir Zlatkovic, Belmont, MA (US);

Shefali Walia, Boxborough, MA (US);

Youssef Mamdouh El-Toukhy, Cairo, EG;

Abdelrahman Alaa Gouda, Cairo, EG;

Alexander A. Alexeyev, Beverly, MA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/156 (2006.01); G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); G06F 1/04 (2013.01);
Abstract

Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.


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