The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Jun. 11, 2020
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Hideki Takeuchi, San Jose, CA (US);

Yung-Hsuan Yang, San Jose, CA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66431 (2013.01); H01L 21/0206 (2013.01); H01L 21/26513 (2013.01); H01L 21/76224 (2013.01); H01L 29/1054 (2013.01);
Abstract

A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region. The method may further include removing at least some of the pad oxide, cleaning the active region to expose an upper surface thereof and define rounded shoulders of the active region adjacent the STI regions having an interior angle of at least 125°, and forming a superlattice on the active region. The superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor circuit including the superlattice.


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