The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Dec. 22, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Shawn P. Fetterolf, Cornwall, VT (US);

Terence B. Hook, Jericho, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/02181 (2013.01); H01L 21/76251 (2013.01); H01L 27/1203 (2013.01); H01L 29/517 (2013.01); H01L 29/66484 (2013.01); H01L 29/7831 (2013.01);
Abstract

Provided are techniques for generating fully depleted silicon on insulator (SOI) transistor with a ferroelectric layer. The techniques include forming a first multi-layer wafer comprising a semiconductor layer and a buried oxide layer, wherein the semiconductor layer is formed over the buried oxide layer. The techniques also including forming a second multi-layer wafer comprising the ferroelectric layer, and bonding the first multi-layer wafer to the second multi-layer wafer, wherein the bonding comprises a coupling between the buried oxide layer and the second multi-layer wafer.


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