The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2023

Filed:

Mar. 12, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Kiyomi Naruke, Sagamihara, JP;

Shinichiro Shiratake, Yokohama, JP;

Mutsumi Okajima, Yokkaichi, JP;

Hidetoshi Saito, Yamato, JP;

Hirofumi Inoue, Kamakura, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); G11C 16/26 (2006.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 23/522 (2006.01); G11C 16/16 (2006.01); G11C 16/24 (2006.01); H01L 23/528 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01);
Abstract

A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.


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