The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2023
Filed:
Aug. 27, 2021
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Eric N. Lee, San Jose, CA (US);
Robert W. Strong, Folsom, CA (US);
William Akin, Morgan Hill, CA (US);
Jeremy Binfet, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/22 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0433 (2013.01); G11C 16/22 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01);
Abstract
A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.