The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2023
Filed:
Aug. 30, 2019
Intel Corporation, Santa Clara, CA (US);
Jason Seung-Min Kim, San Jose, CA (US);
Sundar Ramani, Santa Clara, CA (US);
Yogesh Bansal, Beaverton, OR (US);
Nitin N. Garegrat, San Jose, CA (US);
Olivia K. Wu, Los Altos, CA (US);
Mayank Kaushik, San Jose, CA (US);
Mrinal Iyer, Menlo Park, CA (US);
Tom Schebye, San Carlos, CA (US);
Andrew Yang, Cupertino, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.