The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Mar. 21, 2022
Applicant:

Skyworks Solutions, Inc., Irvine, CA (US);

Inventors:

Timothy Adam Monk, Hudson, NH (US);

Douglas F. Pastorello, Hudson, NH (US);

Krishnan Balakrishnan, Austin, TX (US);

Raghunandan Kolar Ranganathan, Austin, TX (US);

Assignee:

Skyworks Solutions, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); G04F 10/00 (2006.01); H03L 7/085 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1014 (2013.01); G04F 10/005 (2013.01); H03L 7/085 (2013.01);
Abstract

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.


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