The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Oct. 21, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Cheng Ching, Zhubei, TW;

Ka-Hing Fung, Zhudong Township, TW;

Zhiqiang Wu, Chubei, TW;

Carlos H. Diaz, Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/267 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 27/11 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7849 (2013.01); H01L 21/02161 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/324 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/267 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 21/823814 (2013.01); H01L 2029/7858 (2013.01);
Abstract

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.


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