The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Mar. 22, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Richard Knipper, Regensburg, DE;

Frank Daeche, Unterhaching, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/32 (2006.01); H01L 21/3205 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/32 (2013.01); H01L 21/32051 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/544 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68368 (2013.01); H01L 2223/5446 (2013.01);
Abstract

A method for fabricating a semiconductor package includes: providing a semiconductor wafer having opposing first and second sides, the semiconductor wafer being arranged on a first carrier such that the second side of the wafer faces the carrier; masking sawing lines on the first side of the semiconductor wafer with a mask; depositing a first metal layer on the masked first side of the semiconductor wafer by cold spraying or by high velocity oxygen fuel spraying or by cold plasma assisted deposition, such that the first metal layer does not cover the sawing lines, the deposited first metal layer having a thickness of 50 μm or more; singulating the semiconductor wafer into a plurality of semiconductor dies by sawing the semiconductor wafer along the sawing lines; and encapsulating the plurality of semiconductor dies with an encapsulant such that the first metal layer is exposed on a first side of the encapsulant.


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