The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2023

Filed:

Mar. 03, 2021
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shinichi Kuwabara, Ibaraki, JP;

Yasutaka Nakashiba, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/64 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 21/762 (2006.01); H01L 21/74 (2006.01); H01L 49/02 (2006.01); H01L 21/56 (2006.01); H01L 21/8234 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 21/56 (2013.01); H01L 21/743 (2013.01); H01L 21/762 (2013.01); H01L 21/823481 (2013.01); H01L 23/3107 (2013.01); H01L 23/49503 (2013.01); H01L 23/5226 (2013.01); H01L 28/10 (2013.01); H01L 24/48 (2013.01); H01L 2224/4813 (2013.01); H01L 2224/48257 (2013.01);
Abstract

A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.


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