The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Apr. 16, 2021
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Pei-Ting Tsai, Chiayi, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Tsuo-Wen Lu, Kaohsiung, TW;

Min-Teng Chen, Chiayi, TW;

Tsung-Wen Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 27/112 (2006.01); H01L 27/11578 (2017.01); H01L 27/11551 (2017.01); H01L 27/11521 (2017.01); H01L 27/11597 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 28/91 (2013.01); H01L 27/1128 (2013.01); H01L 27/11521 (2013.01); H01L 27/11551 (2013.01); H01L 27/11568 (2013.01); H01L 27/11578 (2013.01); H01L 27/11597 (2013.01); H01L 28/90 (2013.01); H01L 28/60 (2013.01);
Abstract

The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.


Find Patent Forward Citations

Loading…