The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Sep. 10, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Yusuke Niki, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 27/24 (2006.01); H01L 23/522 (2006.01); G11C 11/408 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); G11C 11/4085 (2013.01); G11C 16/08 (2013.01);
Abstract

A memory includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) lines, and second signal lines. A memory cell array includes memory cells. (m+2) or more global signal lines are configured to apply a selection voltage to any of the first signal lines. First transistors are provided to correspond to each of the first signal lines in one-to-one correspondence and are connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups, and are each connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. The first signal lines located at both ends of each of any two of the groups which are adjacent to each other are connected to mutually different ones of the global signal lines.


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