The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Aug. 18, 2020
Imec Vzw, Leuven, BE;
Amey Mahadev Walke, Heverlee, BE;
Liesbeth Witters, Lubbeek, BE;
IMEC VZW, Leuven, BE;
Abstract
The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SiGe() substrate. The method includes: (a) providing a SiGe() substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the SiGe() substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a SiGe() surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the SiGe() surface in the first region; (f) forming a trench in the second region which exposes the SiGe() substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the SiGe() surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.