The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Aug. 30, 2021
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Kelley D. Dobelstein, Seattle, WA (US);
Jason T. Zawodny, Eagle, ID (US);
Kyle B. Wheeler, Meridian, ID (US);
Assignee:
Micron Techology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4074 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G06F 12/06 (2006.01); G11C 8/12 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1006 (2013.01); G06F 12/06 (2013.01); G06F 13/1668 (2013.01); G11C 7/1015 (2013.01); G11C 8/12 (2013.01); G11C 11/408 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G06F 2212/1028 (2013.01); G11C 2207/2209 (2013.01); Y02D 10/00 (2018.01);
Abstract
The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.