The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Jul. 19, 2021
Verisilicon Microelectronics (Shanghai) Co., Ltd., Shanghai, CN;
Verisilicon Holdings Co., Ltd., Cayman Islands, KY;
Verisilicon Microelectronics (Nanjing) Co., Ltd., Nanjing, CN;
VeriSilicon Microelectronics (Shanghai) Co., Ltd., Shanghai, CN;
VeriSilicon Holdings Co., Ltd., Cayman Islands, KY;
VeriSilicon Microelectronics (Nanjing) Co., Ltd., Nanjing, CN;
Abstract
The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.