The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Jan. 12, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhisek Kundu, Bangalore, IN;

Naveen Mellempudi, Bangalore, IN;

Dheevatsa Mudigere, Bangalore, IN;

Dipankar Das, Pune, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2006.01); G06N 5/04 (2006.01); G06N 3/04 (2006.01); G06T 15/00 (2011.01); G06F 9/46 (2006.01); G06N 3/063 (2006.01); G06T 17/20 (2006.01); G06T 15/80 (2011.01); G06T 17/10 (2006.01); G06T 15/04 (2011.01); G06V 10/94 (2022.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 9/46 (2013.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01); G06N 5/04 (2013.01); G06T 15/005 (2013.01); G06T 15/04 (2013.01); G06T 15/80 (2013.01); G06T 17/10 (2013.01); G06T 17/20 (2013.01); G06V 10/94 (2022.01);
Abstract

One embodiment provides for a computing device comprising a parallel processor compute unit to perform a set of parallel integer compute operations; a ternarization unit including a weight ternarization circuit and an activation quantization circuit; wherein the weight ternarization circuit is to convert a weight tensor from a floating-point representation to a ternary representation including a ternary weight and a scale factor; wherein the activation quantization circuit is to convert an activation tensor from a floating-point representation to an integer representation; and wherein the parallel processor compute unit includes one or more circuits to perform the set of parallel integer compute operations on the ternary representation of the weight tensor and the integer representation of the activation tensor.


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