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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11556677 B1

PDFFull Text
Date of Patent:
Jan. 17, 2023

Filed:

Dec. 23, 2020

Scalable runtime validation for on-device design rule checks

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Furkan Turan, Leuven, BE;

Patrick Koeberl, Alsbach-Haenlein, DE;

Alpa Trivedi, Portland, OR (US);

Steffen Schulz, Darmstadt, DE;

Scott Weber, Piedmont, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:

Jaffery Watson Mendonsa & Hamilton LLP

Primary Examiner:

Binh C Tat

Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 21/85 (2013.01); G06N 3/04 (2006.01); H04L 9/08 (2006.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 15/177 (2006.01); G06F 15/78 (2006.01); H04L 9/40 (2022.01); G06F 11/07 (2006.01); G06F 30/331 (2020.01); G06F 9/38 (2018.01); G06F 11/30 (2006.01); G06F 119/12 (2020.01); G06F 21/76 (2013.01); G06N 3/08 (2006.01); H04L 9/00 (2022.01); G06F 111/04 (2020.01); G06F 30/31 (2020.01); G06F 21/30 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 21/73 (2013.01); G06F 21/74 (2013.01); G06N 20/00 (2019.01); G06F 21/71 (2013.01); G06F 21/44 (2013.01);
U.S. Cl.
CPC ...
G06F 21/85 (2013.01); G06F 9/30101 (2013.01); G06F 9/3877 (2013.01); G06F 9/505 (2013.01); G06F 11/0709 (2013.01); G06F 11/0751 (2013.01); G06F 11/0754 (2013.01); G06F 11/0793 (2013.01); G06F 11/3058 (2013.01); G06F 15/177 (2013.01); G06F 15/7825 (2013.01); G06F 15/7867 (2013.01); G06F 30/331 (2020.01); G06F 30/398 (2020.01); G06N 3/04 (2013.01); H04L 9/0877 (2013.01); H04L 63/0442 (2013.01); H04L 63/12 (2013.01); H04L 63/20 (2013.01); G06F 11/0772 (2013.01); G06F 11/3051 (2013.01); G06F 21/30 (2013.01); G06F 21/44 (2013.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 21/575 (2013.01); G06F 21/71 (2013.01); G06F 21/73 (2013.01); G06F 21/74 (2013.01); G06F 21/76 (2013.01); G06F 30/31 (2020.01); G06F 2111/04 (2020.01); G06F 2119/12 (2020.01); G06F 2221/034 (2013.01); G06N 3/08 (2013.01); G06N 20/00 (2019.01); H04L 9/008 (2013.01); H04L 9/0841 (2013.01);
Abstract

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

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