The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Aug. 06, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Tetsuya Arai, Sagamihara, JP;

Junki Taniguchi, Sagamihara, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/135 (2006.01); H03K 3/037 (2006.01); G11C 7/10 (2006.01); H03K 17/687 (2006.01); H03M 9/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/135 (2013.01); G11C 7/1057 (2013.01); H03K 3/037 (2013.01); H03K 17/6872 (2013.01); H03M 9/00 (2013.01);
Abstract

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.


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