The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Jul. 31, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Daniel Sira, Munich, DE;

Domagoj Siprak, Munich, DE;

Jonas Fritzin, Munich, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01L 49/02 (2006.01); H01L 27/06 (2006.01); H01L 23/482 (2006.01); G06F 30/367 (2020.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); G06F 30/367 (2020.01); H01L 23/4824 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/5228 (2013.01); H01L 27/0629 (2013.01); H01L 28/86 (2013.01); H01L 28/90 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6655 (2013.01); H01L 2223/6672 (2013.01);
Abstract

An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.


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