The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Aug. 28, 2020
Applicant:

GE Aviation Systems Llc, Grand Rapids, MI (US);

Inventors:

David Richard Esler, Gloversville, NY (US);

Christopher James Kapusta, Delanson, NY (US);

Arun V. Gowda, Rexford, NY (US);

Weijun Yin, Niskayuna, NY (US);

Liqiang Yang, Pompano Beach, FL (US);

Richard Anthony Eddins, Margate, FL (US);

Assignee:

GE Aviation Systems LLC, Grand Rapids, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); F28F 13/18 (2006.01); H01L 23/373 (2006.01); H05K 7/20 (2006.01); F28F 13/00 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); F28F 13/18 (2013.01); H01L 23/3731 (2013.01); H05K 1/0201 (2013.01); H05K 7/205 (2013.01); H05K 7/20509 (2013.01); F28F 2013/001 (2013.01); H01L 23/3672 (2013.01);
Abstract

A power overlay (POL) module includes a semiconductor device having a first side and an opposing second side, a dielectric sheet having a first side coupled to the semiconductor device second side, and an opposing second side, the dielectric sheet defining an aperture therethrough. The POL module also includes a first conductive layer disposed on the second side of the dielectric sheet and electrically coupled through the aperture to the semiconductor device second surface, a first conductive plate having a first side, and an opposing second side coupled to the first surface of the semiconductor device. The POL module further includes a first heat sink coupled the first side of the conductive plate and a first thermal interface layer disposed between the first conductive plate and the first heat sink.


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