The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Nov. 02, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Abhinav Gaur, Agra, IN;

Neha Bagri, Noida, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 11/263 (2006.01); G06F 11/30 (2006.01); G11C 29/12 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2215 (2013.01); G06F 11/0772 (2013.01); G06F 11/0784 (2013.01); G06F 11/263 (2013.01); G06F 11/3013 (2013.01); G06F 11/3037 (2013.01); G11C 29/12015 (2013.01);
Abstract

A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.


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