The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
May. 18, 2020
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Moo Sung Chae, Cary, NC (US);
Thomas Evan Wilson, Laurel, MD (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/1252 (2006.01); G11C 5/14 (2006.01); H03H 7/06 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); G11C 5/14 (2013.01); H03F 3/45475 (2013.01); H03H 7/06 (2013.01);
Abstract
Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.