The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Feb. 05, 2021
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Weize Chen, Phoenix, AZ (US);

Sameer S. Haddad, San Jose, CA (US);

Bruce B. Greenwood, Gresham, OR (US);

Mark Griswold, Gilbert, AZ (US);

Kenneth A. Bates, Happy Valley, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 29/42324 (2013.01); H01L 29/4933 (2013.01); H01L 29/66825 (2013.01);
Abstract

An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.


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