The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Dec. 22, 2020
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Ying-Chu Yen, Taichung, TW;

Wei-Che Chang, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10855 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 21/76837 (2013.01); H01L 21/76877 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01); H01L 27/10891 (2013.01); H01L 21/02271 (2013.01); H01L 21/31053 (2013.01);
Abstract

A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.


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