The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2023
Filed:
May. 13, 2021
Applicant:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Inventor:
Yi-Chung Liang, Tainan, TW;
Assignee:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/532 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/293 (2013.01); H01L 23/3142 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 23/53209 (2013.01); H01L 24/18 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02372 (2013.01); H01L 2924/186 (2013.01);
Abstract
A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.