Data control circuit for increasing maximum and minimum tolerance values of skew between dqs signal and clock signal during write operation and associated memory device

Abstract

A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.