The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2022
Filed:
Jul. 16, 2020
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventor:
Purnima Narayanan, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/11556 (2017.01); H01L 25/065 (2006.01); H01L 21/50 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 21/50 (2013.01); H01L 25/0657 (2013.01); H01L 27/11582 (2013.01);
Abstract
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.