The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Jun. 03, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yuan He, Boise, ID (US);

Hiroshi Akamatsu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/408 (2006.01); G11C 8/18 (2006.01); G11C 11/4091 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4087 (2013.01); G11C 8/18 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/40603 (2013.01);
Abstract

A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.


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