The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Mar. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ganmei You, Beijing, CN;

Dawei Wang, Beijing, CN;

Ling Liu, Beijing, CN;

Xuesong Shi, Beijing, CN;

Chunjie Wang, Beijing, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); B25J 9/16 (2006.01); G06F 9/30 (2018.01); G06V 10/94 (2022.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
B25J 9/1666 (2013.01); G06F 9/30003 (2013.01); G06F 9/4881 (2013.01); G06F 9/5044 (2013.01); G06F 9/5066 (2013.01); G06V 10/94 (2022.01);
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to improve resource utilization for binary tree structures. An example apparatus to improve resource utilization for field programmable gate array (FPGA) resources includes a computation determiner to identify a computation capability value associated with the FPGA resources, a k-ary tree builder to build a first k-ary tree having a number of k-ary nodes equal to the computation capability value, and an FPGA memory controller to initiate collision computation by transferring the first k-ary tree to a first memory of the FPGA resources.


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