The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Aug. 31, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Darwin A. Clampitt, Wilder, ID (US);

Shawn D. Lyonsmith, Boise, ID (US);

Matthew J. King, Boise, ID (US);

Lisa M. Clampitt, Boise, ID (US);

John Hopkins, Meridian, ID (US);

Kevin Y. Titus, Meridian, ID (US);

Indra V. Chary, Boise, ID (US);

Martin Jared Barclay, Middleton, ID (US);

Anilkumar Chandolu, Boise, ID (US);

Pavithra Natarajan, Santa Clara, CA (US);

Roger W. Lindsay, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 27/11565 (2017.01); H01L 23/522 (2006.01); H01L 27/11597 (2017.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02617 (2013.01); H01L 21/67063 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11565 (2013.01); H01L 27/11597 (2013.01); G11C 16/0483 (2013.01);
Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.


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