The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Aug. 07, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yen-Kuang Chen, Palo Alto, CA (US);

Shao-Wen Yang, San Jose, CA (US);

Ibrahima J. Ndiour, Portland, OR (US);

Yiting Liao, Sunnyvale, CA (US);

Vallabhajosyula S. Somayazulu, Portland, OR (US);

Omesh Tickoo, Portland, OR (US);

Srenivas Varadarajan, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/62 (2022.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 16/535 (2019.01); G06F 16/538 (2019.01); G06F 16/951 (2019.01); G06F 21/44 (2013.01); G06F 21/45 (2013.01); G06F 21/53 (2013.01); G06F 21/62 (2013.01); G06F 21/64 (2013.01); H04L 9/06 (2006.01); G06N 5/02 (2006.01); G06N 3/04 (2006.01); H04L 9/32 (2006.01); H04W 4/70 (2018.01); G06F 16/54 (2019.01); G06N 3/063 (2006.01); G06V 10/20 (2022.01); G06V 10/40 (2022.01); G06V 10/75 (2022.01); G06V 10/44 (2022.01); G06V 20/00 (2022.01); G06V 40/20 (2022.01); G06V 40/16 (2022.01); H04L 67/51 (2022.01); G06T 7/11 (2017.01); G06V 10/96 (2022.01); G06V 30/262 (2022.01); G06K 15/02 (2006.01); G06N 3/08 (2006.01); H04L 67/12 (2022.01); H04N 19/80 (2014.01); H04N 19/46 (2014.01); G06T 7/70 (2017.01); H04W 12/02 (2009.01); H04L 9/00 (2022.01); H04N 19/12 (2014.01); H04N 19/124 (2014.01); H04N 19/167 (2014.01); H04N 19/172 (2014.01); H04N 19/176 (2014.01); H04N 19/44 (2014.01); H04N 19/48 (2014.01); H04N 19/513 (2014.01); G06V 30/194 (2022.01); G06T 7/20 (2017.01); H04N 19/42 (2014.01); H04N 19/625 (2014.01); H04N 19/63 (2014.01); G06T 7/223 (2017.01); H04L 67/10 (2022.01);
U.S. Cl.
CPC ...
G06K 9/6267 (2013.01); G06F 9/4881 (2013.01); G06F 9/5044 (2013.01); G06F 9/5066 (2013.01); G06F 9/5072 (2013.01); G06F 16/535 (2019.01); G06F 16/538 (2019.01); G06F 16/54 (2019.01); G06F 16/951 (2019.01); G06F 21/44 (2013.01); G06F 21/45 (2013.01); G06F 21/53 (2013.01); G06F 21/6254 (2013.01); G06F 21/64 (2013.01); G06K 9/6215 (2013.01); G06K 9/6217 (2013.01); G06K 9/6228 (2013.01); G06K 9/6232 (2013.01); G06K 9/6261 (2013.01); G06K 9/6274 (2013.01); G06K 15/1886 (2013.01); G06N 3/04 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 5/022 (2013.01); G06T 7/11 (2017.01); G06T 7/70 (2017.01); G06V 10/20 (2022.01); G06V 10/40 (2022.01); G06V 10/454 (2022.01); G06V 10/75 (2022.01); G06V 10/96 (2022.01); G06V 20/00 (2022.01); G06V 30/274 (2022.01); G06V 40/161 (2022.01); G06V 40/20 (2022.01); H04L 9/0643 (2013.01); H04L 9/3239 (2013.01); H04L 67/12 (2013.01); H04L 67/51 (2022.05); H04N 19/46 (2014.11); H04N 19/80 (2014.11); H04W 4/70 (2018.02); G06F 2209/503 (2013.01); G06F 2209/506 (2013.01); G06F 2221/2117 (2013.01); G06K 9/6282 (2013.01); G06T 7/20 (2013.01); G06T 7/223 (2017.01); G06T 2207/10016 (2013.01); G06T 2207/20021 (2013.01); G06T 2207/20024 (2013.01); G06T 2207/20052 (2013.01); G06T 2207/20056 (2013.01); G06T 2207/20064 (2013.01); G06T 2207/20084 (2013.01); G06T 2207/20221 (2013.01); G06T 2207/30242 (2013.01); G06V 30/194 (2022.01); G06V 2201/10 (2022.01); H04L 9/50 (2022.05); H04L 67/10 (2013.01); H04N 19/12 (2014.11); H04N 19/124 (2014.11); H04N 19/167 (2014.11); H04N 19/172 (2014.11); H04N 19/176 (2014.11); H04N 19/42 (2014.11); H04N 19/44 (2014.11); H04N 19/48 (2014.11); H04N 19/513 (2014.11); H04N 19/625 (2014.11); H04N 19/63 (2014.11); H04W 12/02 (2013.01);
Abstract

In one embodiment, an apparatus comprises a storage device and a processor. The storage device may store a plurality of compressed images comprising one or more compressed master images and one or more compressed slave images. The processor may: identify an uncompressed image; access context information associated with the uncompressed image and the one or more compressed master images; determine, based on the context information, whether the uncompressed image is associated with a corresponding master image; upon a determination that the uncompressed image is associated with the corresponding master image, compress the uncompressed image into a corresponding compressed image with reference to the corresponding master image; upon a determination that the uncompressed image is not associated with the corresponding master image, compress the uncompressed image into the corresponding compressed image without reference to the one or more compressed master images; and store the corresponding compressed image on the storage device.


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