The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2022

Filed:

Jan. 21, 2021
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Laura K. Pianin, Cambridge, MA (US);

Luke R. Leonard, San Luis Obispo, CA (US);

Wesley D. Viner, San Jose, CA (US);

Guanru Wang, Auburn, MI (US);

Anthony N. Torza, Oakland, CA (US);

James A. Markevitch, Palo Alto, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/324 (2013.01);
Abstract

A method that includes determining a first clock gap for a first block of an integrated circuit based on a performance factor of the first block or an external factor and adjusting a clock signal to the first block based on the first clock gap. The method also includes determining a second clock gap for a second block of the integrated circuit based on (i) the first clock gap and (ii) a performance factor of the second block or the external factor. The second clock gap is different from the first clock gap. The method further includes adjusting the clock signal to the second block based on the second clock gap.


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