The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Dec. 31, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Reinaldo Vega, Mahopac, NY (US);

Takashi Ando, Eastchester, NY (US);

Cheng Chi, Jersey City, NJ (US);

Praneet Adusumilli, Somerset, NJ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/8238 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 29/0653 (2013.01); H01L 29/6684 (2013.01); H01L 29/78648 (2013.01); H01L 21/8238 (2013.01); H01L 27/1203 (2013.01);
Abstract

A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.


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