The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Jun. 09, 2021
Applicant:

Upi Semiconductor Corp., Hsinchu County, TW;

Inventors:

Nobuyuki Shirai, Hsinchu County, TW;

Chun-Hsu Chang, Hsinchu County, TW;

Ming-Hung Chou, Hsinchu County, TW;

Assignee:

uPI Semiconductor Corp., Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 21/033 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01);
Abstract

Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.


Find Patent Forward Citations

Loading…