The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2022
Filed:
Apr. 27, 2021
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Hae-Chang Lee, Los Altos, CA (US);
Jaeha Kim, Los Altos, CA (US);
Brian Leibowitz, San Francisco, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 23/00 (2006.01); G01R 29/26 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 29/26 (2013.01); G01R 31/31709 (2013.01); G01R 31/31725 (2013.01);
Abstract
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.