The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Sep. 22, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventor:

Wein-Town Sun, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11524 (2017.01); H01L 29/788 (2006.01); H01L 49/02 (2006.01); G06F 7/58 (2006.01); H03K 3/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); G06F 7/588 (2013.01); H01L 28/40 (2013.01); H01L 29/7884 (2013.01); H03K 3/84 (2013.01);
Abstract

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.


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