The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Oct. 30, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Seungwon Im, Seoul, KR;

Jeungdae Kim, Gimpo, KR;

Oseob Jeon, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 23/3114 (2013.01); H01L 23/49506 (2013.01); H01L 23/49568 (2013.01); H01L 23/49861 (2013.01); H01L 24/48 (2013.01); H01L 2224/80895 (2013.01);
Abstract

In one general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface. The package can also include a semiconductor die coupled with the first surface of the die attach paddle. The package can further include a direct-bonded-metal (DBM) substrate. The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle; and a second metal layer disposed on the second surface of the ceramic layer. The second metal layer can be exposed external to the semiconductor device package. The second metal layer can be electrically isolated from the first metal layer by the ceramic layer.


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