The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2022
Filed:
Jul. 22, 2020
Applicant:
Rambus Inc., San Jose, CA (US);
Inventor:
Keith Lowery, Garland, TX (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 8/453 (2013.01); G06F 9/3004 (2013.01); G06F 9/3889 (2013.01); G06F 9/50 (2013.01); G06F 12/023 (2013.01); G06F 2209/502 (2013.01); G06F 2212/2542 (2013.01); Y02D 10/00 (2018.01);
Abstract
A method and system for thread aware, class aware, and topology aware memory allocations. Embodiments include a compiler configured to generate compiled code (e.g., for a runtime) that when executed allocates memory on a per class per thread basis that is system topology (e.g., for non-uniform memory architecture (NUMA)) aware. Embodiments can further include an executable configured to allocate a respective memory pool during runtime for each instance of a class for each thread. The memory pools are local to a respective processor, core, etc., where each thread executes.