The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Sep. 18, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Bongsoon Lim, Seoul, KR;

Sang-Wan Nam, Hwaseong-si, KR;

Sang-Won Park, Seoul, KR;

Sang-Won Shim, Seoul, KR;

Hongsoo Jeon, Suwon-si, KR;

Yonghyuk Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 27/11556 (2017.01); H01L 27/11526 (2017.01); G11C 8/14 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 27/11519 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01);
Abstract

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.


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