The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Sep. 21, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Karthik Shanmugam, Singapore, SG;

Jun Zhai, Cupertino, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/16 (2006.01); H05K 1/18 (2006.01); H01L 21/56 (2006.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/568 (2013.01); H01L 23/485 (2013.01); H01L 23/5383 (2013.01); H01L 25/165 (2013.01); H01L 25/167 (2013.01); H05K 1/185 (2013.01);
Abstract

One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.


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